⚡Spec
🔧Design
🔬Verify
⏱️Lab
🏭Fab
🧪Test
🤖App
🚀Indie
🔄Loop
🎓Origin
📡Connect
ankit@silicon ~ pipeline
Open to exciting DV / Semiconductor roles
Ankit Gupta

Ankit Gupta

Design Verification Engineer · PCIe · UVM · VIIT Pune

🔬 DV Engineer by day × 🚀 Indie Builder by night
guptaankit13013@gmail.com LinkedIn +91-75176-91447
vsim> run_test …▊
0+YOE DV
UVMEnvs
Pre-SiSign-off
0Patents
View My Work Get in Touch
🔧 DESIGN PHASE — Architecting the Engineer
About Me

Every great chip starts with a spec

PHASE 01 // BOOT PWR_OK · RESET_N = 1

VIIT Pune · E&TC & IoT

Studied Electronics & Telecommunication at VIIT, Pune, serving as Technical Head of IoT Forum and CMA Head of Lighthouse Magazine. Won national-level hackathons and robotics competitions.

Invented hardware architectures yielding 2 granted patents (Patent #406325 for VORA Robotic Arm & Patent #406326) — forging a solid grounding in digital logic, timing closure, and micro-architectures.

VIIT Pune 2 Granted Patents IoT Forum Head Robotics
Inspect College Lab & Patents
PHASE 02 // VERIFY UVM · PRE-SILICON · SIGN-OFF

Enterprise Silicon · ASIC Verification

4+ years closing pre-silicon verification for high-throughput networking and storage ASIC IPs at Chelsio Communications, Bangalore. Built production UVM environments for high-speed serial and on-chip protocols.

Authored extensive directed & constrained-random test suites, automated regression triage, caught critical pre-silicon bugs prior to tape-out, and drove functional & code coverage to sign-off closure. Recognized with 4 corporate awards.

SystemVerilog UVM PCIe Serial protocols 4 Awards
Explore Silicon Verification Flow
PHASE 03 // SHIP HTTP/3 · 200 OK · PROD

Indie Builder · Software Velocity

By night and weekend, I channel silicon precision into building and shipping full-stack developer tools and web applications. Creator of DV Architect — a visual UVM environment IDE that streamlines testbench construction.

Also shipped SiliconShorts (curated daily semiconductor news), GuruStats (audited trade-call terminal), Watchlist Manager PWA (offline-first investor tool), and SearchGap Analyzer. Bringing the speed and craft of modern web engineering to hardware domains.

DV Architect SiliconShorts GuruStats Shopify & SaaS Full-Stack PWA
View Indie Products & Tools
STAGE 01 // BOOT
0+
Years in ASIC DV
UVM environments for high-speed serial and on-chip protocols, taken through pre-silicon sign-off.
0
Granted Patents
Patent #406325 (VORA Robotic Arm) and Patent #406326 — innovations in IoT-connected hardware systems.
0
Company Awards
Recognized for verification milestones across protocol work, coverage closure, regression debug, and bring-up support.
UVM
Testbenches
Directed and constrained-random suites across multi-clock protocols, with coverage taken to sign-off.
🔬 VERIFICATION — Catching bugs before tape-out
Experience

Where I've verified

4+ years closing verification for enterprise ASIC products — one timeline, top to bottom.

Current Role · 4+ YOEJun 2022 – Present

Design Verification Engineer

Chelsio Communications Pvt. Ltd. · Bengaluru
  • Built UVM environments for protocol and subsystem verification, and took functional and code coverage through to tape-out closure.
  • Wrote directed and constrained-random tests, and found pre-silicon RTL bugs before tape-out.
  • Automated Python regression and triage so debug cycles got shorter; verified serial peripherals (SMBus, I2C, UART) and supported FPGA bring-up.
🏆 Verification milestone 🏆 Coverage milestone 🏆 Regression milestone 🏆 Bring-up milestone
Serial linksCoverage closedPre-silicon
Subsystem sketch ↓Serial protocol ↓Link training ↓
See this journey in waveforms ↓
Impact at a Glance
Pre-SiBugs before tape-out
ClosedCoverage sign-off
SerialHigh-speed links
FasterRegression debug

E-Commerce & SaaS chapters (Birdchime · Tradexa) live in E-Commerce & Indie Journey →

⏱️ SILICON LAB — Waveforms, clocks & state machines
Interactive Lab · Verification Engineering

My verification journey, live in waveforms

A public-spec sketch of protocol verification — not a product trace. Subsystem checks, Gen5-class serial, link training, then bring-up.

Stage 1/4 · Subsystem UVMProtocol blocksMulti-agent testsCoverage sign-off

Public-spec sketch of subsystem verification with UVM. Not a product trace.

verification_sim.vcd — stylized DVE● LIVE
t = 0 ns · public-spec sketch · link in L0

Illustrative simulation — randomized signal model for demo. No proprietary trace data.

PCIe Link Training & Status State Machine (LTSSM)
Detect Polling Configuration L0 L0s L1 L2 Recovery Hot Reset Disable Loopback
L0 — Link Operational

Full-speed line-rate traffic — the active operational link state. Click any state for details.

Public-spec sketch of an operational link. Not a trace from a product.

Simplified reference — standard PCIe specification states.

Fundamentals I still use reading RTL
Y = 0 · AND(0,0)

4:1 MUX — select lines pick one input.

Y = I0 = 1

3:8 decoder — one-hot output. Type 0-7.

101 → 00100000

8b/10b concept: 0xBC → K28.5 comma (illustrative).

Rising-edge D FF. Toggle D, then pulse CLK.

Q = 0 · Qn = 1
Clock playground — illustrative rates
Period 10.00ns · 100MHz · Duty 50%
🏭 FABRICATION — The layers that build the chip
Skills

Silicon stack, one engineer

🔬
Silicon & Verification
ASIC verification & silicon design
DV Core
SystemVerilog Verilog UVM
PCIe I2C SMBus UART TCP/IP
VCS DVE Cadence VIP Verilator Python Bash Tcl Linux
Silicon ↔ Software
🚀
Builder Stack
What I use for side projects & products
DEPLOYMENT
Firebase PWA Vercel
FRONTEND
React.js Tailwind CSS Chart.js Shopify Liquid
BACKEND / APIs
Node.js Express FastAPI PostgreSQL
LANGUAGES
JavaScript Python HTML/CSS C/C++ SQL
HARDWARE / IoT
Arduino ESP8266/ESP32 MQTT KiCAD Fusion 360
🧪 TEST — Proving the design works
DV Projects

Tools from the silicon side

↓ Scroll down — the story moves sideways →

STEP 1 / 5 · BOOT
TEST PHASE · horizontal story

Every tool began as one waveform

keep scrolling ↓ · the story walks the track →

PASS ✓SHIPPED
⭐ Flagship Project

DV Architect

A visual, drag-and-drop IDE for designing UVM testbench architectures. Drag in an agent, drop a scoreboard, wire them up — get syntactically correct SystemVerilog in seconds. The game-changer: Code2Visual — import any existing UVM codebase and get an instant interactive block diagram.

PythonPyQtSystemVerilog ParserASTCross-platform
Visit Website →
PASS ✓TLP
🧬 Web + VS Code Extension

UVM Blueprint

A web-based UVM architecture visualizer — paste a GitHub repo URL, and it compiles and renders your entire testbench structure as an interactive diagram. Click components to highlight signal paths, pan & zoom the canvas. Also ships as a VS Code extension for fully private, offline local visualization.

PythonJavaScriptSystemVerilogVS Code ExtensionCanvas Rendering
Try UVM Blueprint →
PASS ✓LIVE FEED
Semiconductor Feed

SiliconShorts

A short-form semiconductor news feed — swipeable reels + filterable digest. Curated chip-industry, AI-in-silicon, and DV picks from SemiEngineering, SemiWiki & SemiAnalysis. Built for engineers who want their semi news in 60-second bites.

Next.jsFirebaseFirestoreTailwind CSSGoogle Auth
Visit SiliconShorts →
COVERAGE CLOSURE

Three tools, zero flakes.

Each one passed the same gate: reproducible, covered, shipped.

Open the waveform lab →See the builder side →
CLOCK-DOMAIN CROSSING: HARDWARE → E-COMMERCE & SOFTWARE
PHASE 01 / 04 · SILICON TAPE-OUT ✓ pre-silicon · high-speed serial

Tape-out complete.

4+ years closing pre-silicon verification for enterprise ASIC products at Chelsio Communications. UVM environments for protocol and subsystem verification on high-speed serial links.

Coverage to sign-off Pre-silicon bugs found High-speed serial
Domain clk_asic locked · Scroll to initiate clock domain crossing ↓
PHASE 02 / 04 · CDC SYNCHRONIZATION… Dual-Flop Sync ⇄ Async FIFO Handshake

Crossing clock domains.

Bridging nanosecond ASIC clock domains into modern software velocity. Dual-flop synchronizers and async FIFOs resolve metastability—transferring rigorous verification discipline into high-reliability software architecture.

clk_asicSilicon domain
2-FLOP FIFO SYNC
clk_web60 Hz (Real-Time)
Metastability resolved · Bridging into E-Commerce scale ↓
PHASE 03 / 04 · E-COMMERCE FOUNDATION Shopify Ecosystem · Tradexa & Birdchime

E-Commerce & Merchant Scale.

Applying engineering precision to consumer e-commerce. Built custom merchant support bots from scratch, managed cross-border logistics, and helped teams achieve 100+ five-star reviews on the Shopify App Store.

⭐ 100+ 5-Star Shopify Reviews 🤖 Automated Support Bots 📦 D2C Retail Brand Scaling
★★★★★ 5.0 / 5.0 Rating · 100+ Verified Merchant Reviews
E-Commerce synchronized ✓ · Ready for Indie Domain ↓
PHASE 04 / 04 · FULL-STACK & INDIE DOMAIN ✓ Real-Time SaaS · Live Shipped Products

Hardware Rigor Meets Live Shipping.

The dual-domain loop in action: silicon-grade precision driving user-facing web applications. Ready to explore Birdchime, Tradexa, SearchGap Analyzer, Watchlist Manager, GuruStats, SiliconShorts, and DV Architect.

🚀 4+ Live SaaS Products ⚡ Sub-10ms Live Latency 🧠 Dual-Domain Engineering
Explore Indie Journey ↓
🚀 INDIE — The journey continues. Same engineer, new layer.
E-Commerce & Indie Builder Journey

Where silicon precision meets e-commerce scale

From 4+ years verifying silicon to driving Shopify merchant wins (100+ 5★ reviews) & shipping live products → Scroll to explore

STEP 1 / 6 · CH 1 · THE E-COM PIVOT
Chapter 1 · The Pivot

Silicon Rigor →
E-Commerce Scale

From verifying high-speed serial silicon by day to scaling e-commerce support, automating catalogs, and shipping user-facing tools.

🔬 ASIC DV → 🛍️ Work Experience → 🚀 Shipped Apps
💼 WORK EXPERIENCE · Shopify SaaS

Product Support Specialist & SaaS Builder

Birdchime Technologies · Feb 2023 – Aug 2023
  • SaaS product support for global Shopify merchants. Built automated support bot and merchant documentation from scratch.
  • Directly drove the app to 100+ five-star reviews on the Shopify App Store through rapid technical resolution.
  • Identified merchant UX bottlenecks and collaborated with engineers on checkout & storefront app features.
💼 WORK EXPERIENCE · B2B Retail & E-Com

Technical Product Support Intern

Tradexa Technologies · May 2021 – Dec 2021
  • Led merchant onboarding, technical account management, and pre-sales solutions for fast-growing retail brands.
  • Engineered Web & API scraping workflows to ingest and sanitize product databases with thousands of SKUs.
  • Collaborated with QA on rigorous mobile and web checkout testing passes.
SHIP ✓LIVE PRODUCT
🛠️ SHIPPED PRODUCT · E-Commerce Analytics

SearchGap Analyzer

Tracks zero-result searches on Shopify stores — helping merchants recover lost revenue by identifying product gaps customers search for but cannot find. Fixes catalog relevance and turns missed queries into revenue.

ShopifyE-Commerce AnalyticsJavaScriptSEORevenue Recovery
Visit Website →
SHIP ✓LIVE PWA
🛠️ SHIPPED APP · Cross-Platform PWA

Watchlist Manager

A cross-platform Progressive Web App to track every movie, series, anime & documentary across all streaming platforms — in one place. Search via TMDB, sync across devices with Google Auth + Firebase, bulk-import from YouTube, and get viewing insights.

FirebaseTMDB APIPWAGoogle AuthJavaScriptTailwind CSSSwipe Gestures
Visit Website →
SHIP ✓LIVE DEV TOOL
🛠️ SHIPPED DEV TOOL · Visual UVM IDE

DV Architect & SiliconShorts

DV Architect: A browser-based visual UVM IDE enabling verification teams to design, assemble, and export SystemVerilog/UVM testbench architectures visually. Coupled with SiliconShorts: curated daily semiconductor insights for engineers.

UVM / SystemVerilogNext.jsVisual IDECanvas APISemiconductor Media
Open DV Architect → Open SiliconShorts →
SHIP ✓LIVE AUDIT
🛠️ SHIPPED APP · Trade-Call Audit

GuruStats

An audit terminal for public F&O influencer calls. Every tip is archived the moment it is posted, then scored against real exchange prices — target hit first is a win, stop-loss hit first is a loss. No deleted losses, no retroactive edits.

Market DataAudit LedgerTelegram / XJavaScript
Open GuruStats →
Builder Impact
0+Products Shipped
0Live Web Apps
0+Users Served
∞Curiosity
Both journeys run in parallel. Same engineer. Different layers of the stack.
🔄 THE LOOP — Continuous Engineering Substrate
Engineering Philosophy

The loop continues

Verification taught me coverage. Building teaches me users. The same debug loop — reproduce, isolate, fix, regress — now ships products at scale.

🔬
01. VERIFY
Edge cases, assertions & coverage closure
💻
02. BUILD
Clean architecture, UI/UX & performance
🚀
03. SHIP
Live production velocity & real users
📊
04. LEARN
Telemetry, feedback & regression passes
4+ YOEASIC Verification
100+Shopify 5★ Reviews
5+Products Shipped
2Granted Patents
Revisit Silicon Lab Let's Build Together →
🎓 ORIGIN — Where the substrate was formed
College Life

VIIT Pune

BOOT ROM — where it compiled · AND → OR → FF → UART

🎯 Swadeshi Microprocessor Challenge (Quarter-Finalist) ✦ 🥇 1st Prize PYP Solution 20 (AIT Pune) ✦ 🌟 AIR 5 Indian Science Festival (IISER Pune · 800+ Projects) ✦ 🥈 1st Runner Up Mindspark (COEP Pune · 50+ Teams) ✦ 🎯 Swadeshi Microprocessor Challenge (Quarter-Finalist) ✦ 🥇 1st Prize PYP Solution 20 (AIT Pune) ✦ 🌟 AIR 5 Indian Science Festival (IISER Pune · 800+ Projects) ✦ 🥈 1st Runner Up Mindspark (COEP Pune · 50+ Teams)
Education
Vishwakarma Institute of Information Technology
B.Tech — Electronics & Telecommunication (E&TC)
4-Year
Program
Pune
Campus
E&TC
Branch
Digital Electronics Microprocessors & Embedded Systems VLSI Design IoT & Robotics
COMPETITIONS & NATIONAL RECOGNITION

Major Achievements & Awards

4 Key Honors
🎯 QUARTER-FINALIST 2021 · National
⚡

Swadeshi Microprocessor Challenge

Ministry of Electronics & IT (MeitY) & IIT Madras

Quarter-Finalist in the prestigious nationwide initiative to architect innovative hardware solutions on indigenous RISC-V microprocessors (SHAKTI & VEGA SoC ecosystems).

RISC-V Architecture MeitY Govt of India FPGA Prototype
🥇 1ST PRIZE WINNER PYP 2020
🏆

1st Prize — PYP Solution 20

Army Institute of Technology (AIT, Pune)

Secured 1st Prize across competing engineering colleges for technical design, circuit architecture, and real-time execution of embedded hardware solution.

1st of All Teams AIT Pune Trophy Embedded Systems
🌟 ALL INDIA RANK 5 (AIR 5) 800+ Projects
🎖️

AIR 5 PYP — Indian Science Festival

IISER Pune (Indian Institute of Science Education & Research)

Ranked AIR 5 among 800+ projects nationwide for the VORA Voice Operated Robotic Arm system. Directly led to granted Patent #406325.

Top 0.6% in India 800+ Pan-India Teams Granted Patent #406325
🥈 1ST RUNNER UP 50+ Teams
🔮

Mindspark — IoT & AR Competition

COEP Pune (College of Engineering Pune)

1st Runner-Up among 50+ college teams in the IoT and Augmented Reality Quiz Competition at COEP's flagship national technical festival Mindspark.

1st Runner-Up 50+ College Teams COEP Mindspark
Leadership Roles
Technical Head
IoT Forum, VIIT
Aug–Dec 2020
CMA Head
Lighthouse Magazine, VIIT
Aug 2020–Jan 2021
IT Manager
EESA VIIT (Electronics & Engineering Students)
Aug 2020–May 2021
College Ambassador
Techfest, IIT Bombay
—
Publicity Head
Gandharva — Annual Cultural Fest, VIIT
—
Volunteer
NSS — National Service Scheme, VIIT
—
🎪
Annual Cultural Fest · VIIT
Publicity Head — Gandharva

Led the full publicity and outreach campaign for VIIT's annual cultural fest — social media strategy, promotional design, event announcements, and student engagement across platforms.

📄 Published Research — First Tape-out
VORA: A Voice Operated Robotic Humanoid Arm
NodeMCU ESP8266 + Google Assistant + IFTTT + Adafruit Cloud + MQTT. Custom PCB designed on KiCAD. Presented at national level at IISER Pune — AIR 5 among 800+ projects. Led to Patent #406325.
📜
VORA Robotic Arm System
Patent #406325
📜
IoT Connected System
Patent #406326
📡 CONNECT — Ready for the next tape-out
LINK UP · L0 STATE · READY FOR NEXT TAPE-OUT RESPONSE TIME < 1 HR
Let's Connect

Ready for the next tape-out?

Whether it's a DV role, a collaboration on a side project, or just a chat about PCIe and UVM — I'm always up for a good conversation.

Let's build together →
Email LinkedIn Phone DV Architect